The most common form of wireless communication involves the modulation of information onto a carrier wave of electromagnetic radiation at so-called radio frequency, or RF (generally, in the range 3 KHz to 300 GHz). A critical operation in the transmission and reception of information via RF carriers is frequency up-conversion and down-conversion, respectively. Accordingly, a key circuit component in a transmitter or receiver is a frequency mixer. A mixer is a nonlinear electrical circuit that shifts an information signal from one frequency to another, also known as heterodyning. For example, a mixer in a receiver may convert a signal at an RF frequency fRF by mixing it with a lower frequency signal from a Local Oscillator fLO, yielding the heterodynes (fRF+fLO) and (fRF−fLO). The former of these is typically discarded by filtering, and the latter is amplified and processed. In a superheterodyne receiver, the recovered signal is an Intermediate Frequency (IF) signal, which may undergo another frequency down-conversion before information is extracted from it. Direct conversion receivers convert an RF signal directly to DC, generating a Baseband (BB) signal, using only one frequency mixing operation. Mixers are also used in transmitters to up-convert a modulated signal to a desired RF transmission frequency. However, for simplicity and clarity, embodiments of the present invention are explained herein in the context of a receiver, frequency down-converting an RF signal.
Modern mixer design is challenging. Requirements of high bandwidth and high Signal to Noise and Distortion Ratio (SNDR) become more stringent with each generation of wireless communication protocols (e.g., 5G). Additionally, all circuits in portable, battery-powered devices, such as smartphones and other User Equipment operative in wireless communication networks, have limited silicon area and strict power budgets. A passive mixer architecture is popular in many receiver designs, due to its intrinsic wide bandwidth, low power, and low noise.
A passive mixer can be deployed as a frequency down-converting stage in a direct conversion receiver, where it becomes a critical block for the linearity of the receiver chain. Nonlinearity of switching transistors in a down-conversion mixer is a known source of distortion, particularly second and third order distortion. Accordingly, numerous approaches have been developed to improve linearity. In one such technique, known as bootstrapping, the gate terminal of a transistor is driven with a higher voltage that depends on the input (and/or output) signal, to approach a constant (signal independent) on-resistance. For example, if a transistor receives a voltage of VDD+Vin at the gate terminal, and an input signal voltage of Vin at the source terminal, then the gate-to-source voltage is Vgs=Vg−Vs=(VDD+Vin)−Vin=VDD, a constant value. A constant Vgs over all input voltages reduces signal modulation of the on-resistance in the transistor conduction channel. Bootstrap circuits solve two problems associated with a one-transistor switch: the limited input range due to the threshold voltage, and the switch resistance variation. For more information, see Chen, et al., “A High-performance Bootstrap Switch for Low Voltage Switched-Capacitor Circuits,” 2014 IEEE International Symposium on Radio-Frequency Integration Technology (2014), the disclosure of which is incorporate herein by reference in its entirety.
The combination of a passive, current driven mixer and bootstrapping the mixing transistors in the mixer is known to reduce the nonlinearities of a receiver. Also, as well known in the electronic arts, improved performance, stability, linearity, and noise immunity may be achieved by implementing circuits in a differential configuration. That is, rather than representing a signal value as a single voltage referenced to ground (single-ended), the circuit is configured as mirror-image positive and negative sub-circuits, and the signal value is represented as the difference of two voltages. As used herein, with respect to differential circuits, the terms “positive” and “negative” are terms of reference used to identify the two complimentary halves of a differential circuit, or the dual inputs or outputs (e.g., “positive input” or “negative output”). The terms do not indicate any value of a voltage with respect to zero volts.
FIG. 1 depicts one known configuration of a bootstrapped, passive, current driven, differential, frequency conversion IQ mixer. Differential RF inputs RFN and RFP are input to two differential pairs of mixing transistors in each of In-phase (I) and Quadrature (Q) mixer circuits. The mixing transistors are clocked with Local Oscillator (LO) clocks LOPI, LONI, LOPQ and LONQ. The Q clock signals are phase-shifted from the I clock signals by 90°. Operation of the IQ mixer is well known in the art and is not further described herein. The mixing transistors are bootstrapped for improved linearity. In the circuit of FIG. 1, this comprises buffering the positive and negative RF inputs, each buffer having a gain αBOOT, and adding the buffered input to the LO clock signal prior to the gate terminal of the mixing transistors. The gate terminals of the transistors are thus driven with a higher voltage that varies with the input signal, maintaining a more constant Vgs and hence on-resistance.
Due to the current driven architecture, the base band circuits provide a very low load impedance at the mixer output, reducing significantly the mixer output voltage swing. This makes a bootstrap by the output IF signal superfluous.
FIG. 2 depicts a conceptual view of one technique to bootstrap a mixing transistor. FIG. 2 depicts a capacitor C1; the mixing transistor, with parasitic capacitance CP and equivalent on-resistance Ron; and idealized switches SW1-SW5, operated by different phases of a clocking signal. During a first phase φ1 of the clock signal, switches SW1, SW2, and SW4 are closed, and switches SW3 and SW5 are open. This connects the capacitor C1 across the supply voltage, charging it, and grounds the gate of the mixing transistor, turning it off. During the alternate phase φ2 of the clock, switches SW1 and SW2 open, disconnecting the capacitor C1 from the supply voltage, and switch SW4 opens to remove the ground from the gate of the transistor. Meanwhile, switches SW3 and SW5 close, connecting the capacitor C1 between the source terminal of the transistor (where the input voltage Vin is applied) and the gate terminal. This applies to the gate terminal the sum of the (unbuffered) input voltage Vin and the voltage on the capacitor, which is the supply voltage; hence Vg=VDD Vin. As discussed above, the gate-to-source voltage Vgs is Vg−Vs=(VDD+Vin)−Vin=VDD. Hence, Vgs, and the transistor equivalent on-resistance Ron, is largely constant, and independent of the input signal, yielding very good linearity.
FIG. 3 depicts a schematic implementing the conceptual view of FIG. 2. The signal Clk_N is the inverted signal of Clk. During a first phase, when Clk=1 and Clk_N=0, the capacitor C1 is charged to the supply voltage value by M1 and M2 being closed (and M3 and M5 being open to isolate C1 from the transistor), and the mixing transistor is off due to M4 being closed and grounding the gate terminal. During the opposite phase, when Clk=0 and Clk_N=1, the capacitor C1 is disconnected from the power rails and connected between the buffer and gate terminal of the mixing transistor. This applies to the gate terminal the sum of the supply voltage (on the capacitor) and the amplified input voltage αBOOT*VRF. The amplification by αBOOT (nominally 0.5) is required in applying this bootstrap technique to a passive mixer to obtain the desired amplitude of signal to linearize the mixing transistor, and to reduce crosstalk.
To implement the bootstrapping of mixing transistors depicted in FIG. 3 into the passive mixer circuit of FIG. 1 would require one switch network (M1-M5), one capacitance, and one active stage (buffer) for each mixing transistor. This would necessarily entail:                Additional capacitance at the input of the passive mixer switch proportional to the number of buffering stages, introducing loss in the signal path;        Additional power for each buffering stage and number of switches to be driven by the clock circuits;        Additional complexity in the clock (and inverse clock) distribution;        Additional silicon area due to the buffering stage and bootstrap switch network and capacitance for each switch of the passive mixer; and        Additional mismatch sources, contributing to the even order differential-mode distortion.        
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches descried in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.